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PEDD514265ESL-01 This version : Jan. 2001
Semiconductor
MSM514265E/ESL
262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
Preliminary
DESCRIPTION
The MSM514265E/ESL is a 262,144-word x 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514265E/ESL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM514265E/ESL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The MSM514265ESL (the Self-refresh version) is specially designed for lower-power applications.
FEATURES
* * * * * * * * * 262,144-word x 16-bit configuration Single 5V power supply, 10% tolerance Input Output Refresh : TTL compatible, low input capacitance : TTL compatible, 3-state : 512 cycles/8ms, 512 cycles/128 ms (SL version)
Fast page mode with EDO, read modify write capability CAS before RAS refresh, hidden refresh, RAS-only refresh capability CAS before RAS self-refresh capability (SL version) Package options: 40-pin 400mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM514265E/ESL-xxJS) xx indicates speed rank. 44/40-pin 400mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514265E./ESL-xxTS-K)
PRODUCT FAMILY
Access Time (Max.) Family MSM514265E/ESL tRAC 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns tOEA 15ns 20ns Cycle Time (Min.) 104ns 124ns Power Dissipation Operating (Max.) 633mW 578mW Standby (Max.) 5.5mW/ 1.1mW (SL version)
PEDD514265ESL-01
MSM514265E/ESL
PIN CONFIGRATION (TOP VIEW)
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 VCC 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 13 NC 14 WE 15 RAS 16 NC 17 A0 18 A1 19 A2 20 A3 21 VCC 22
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23
VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
40-Pin Plastic SOJ 44/40-Pin Plastic TSOP (K Type)
Pin Name A0 - A8 RAS LCAS UCAS DQ1-DQ16 OE WE VCC VSS NC
Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
PEDD514265ESL-01
MSM514265E/ESL
BLOCK DIAGRAM
WE RAS LCAS UCAS
Column Address Buffers Internal Address Counter Row Address Buffers Timing Generator I/O Controller I/O Controller 9 9 Column Decoders 8 Output Buffers 8
OE
DQ1DQ8
8 I/O Selector Input Buffers 8
A0A8
Refresh Control Clock
Sense Amplifiers
16
16 Input Buffers
8 9 9 Row Decoders Word Drivers Memory Cells 8
8
DQ9DQ16
Output Buffers 8
VCC
On Chip VBB Generator
VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H DQ Pin Function Mode DQ1-DQ8 High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ9-DQ16 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
* : "H" or "L"
PEDD514265ESL-01
MSM514265E/ESL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage VCC supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Rating -0.5 to VCC + 0.5 -0.5 to 7.0 50 1 0 to 70 -55 to 150 Unit V V mA W C C
*: Ta = 25C
Recommended Operating Conditions
(Ta = 0C to 70C)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 4.5 0 2.4 -0.5
*2
Typ. 5.0 0
Max. 5.5 0
Unit V V
*1
VCC VSS VIH VIL
VCC + 0.5
0.8
V V
Notes:
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied).
Capacitance
(VCC = 5V 10%, Ta = 25C, f=1MHz)
Parameter Input Capacitance (A0 - A8) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol Typ. Max. 5 7 7 Unit pF pF pF
CIN1 CIN2 CI/O
PEDD514265ESL-01
MSM514265E/ESL
DC Characteristics
(VCC = 5V 10%, Ta = 0C to 70C)
MSM514265 E/ESL-60 Min. Output High Voltage Output Low Voltage Input Leakage Current VOH VOL ILI IOH = -5.0mA IOL = 4.2mA 0V VI VCC+0.5V; All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS VCC - 0.2V RAS cycling, CAS = VIH, tRC = Min. RAS = VIH, CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, CAS cycling, tHPC = Min. tRC = 125s CAS before RAS tRAS = 1s RAS 0.2V, CAS 0.2V, 2.4 0 - 10 Max. VCC 0.4 10 MSM514265 E/ESL-70 Min. 2.4 0 - 10 Max. VCC 0.4 10 V V A
Parameter
Symbol
Condition
Unit Note
Output Leakage Current Average Power Supply Current (Operating)
ILO
- 10
10
- 10
10
A
ICC1

115 2 1 200 115

105 2
mA
1,2
mA 1 200 105 A mA
1 1,5 1,2
Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh)
ICC3
ICC5
5
5
mA
1
ICC6
115
105
mA
1,2
ICC7
115
105
mA
1,3
ICC10
300
300
A
1,4 ,5
ICCS
300
300
A
1,5
Notes: 1. 2. 3. 4. 5.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH.
VCC - 0.2V VIH VCC + 0.5V, - 0.5V VIL 0.2V. SL version.
PEDD514265ESL-01
MSM514265E/ESL
AC Characteristic (1/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3
MSM514265 E/ESL-60 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (SL version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH 104 135 25 68 0 5 0 0 0 0 1 40 60 60 10 10 10 10 40 5 35 5 14 12 0 10 Max. 60 15 30 35 15 15 15 15 15 50 8 128 10,000 100,000 10,000 45 30 MSM514265 E/ESL-70 Min. 124 160 30 78 0 5 0 0 0 0 1 50 70 70 13 13 10 10 45 5 40 5 14 12 0 10 Max. 70 20 35 40 20 20 20 20 20 50 8 128 10,000 100,000 10,000 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 13 13 15 16 7,8 7,8 7 7 3 4, 5, 6 4,5 4,6 4,13 4 4
Parameter
Symbol
Unit
Note
PEDD514265ESL-01
MSM514265E/ESL
AC Characteristic (2/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3
MSM514265 E-60 Min. Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tRASS 0 10 30 0 0 0 0 10 10 7 10 10 10 10 10 0 10 15 35 50 80 55 5 5 10 100 Max. MSM514265 E-70 Min. 0 13 35 0 0 0 0 13 10 7 13 10 10 13 13 0 13 20 45 60 95 65 5 5 10 100 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s 10 10 10 10 12 12 13 16 14 11,12 11,12 12 9,12 9 10,12 12 12 12
Parameter
Symbol
Unit
Note
tRPS
110 - 40
130 - 50
ns
16
tCHS
ns
16
PEDD514265ESL-01
MSM514265E/ESL
Notes:
1.
A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 2ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF. The output timing reference levels are VOH = 2.0V (IOH = -2mA) and VOL = 0.8V (IOH = 2mA). Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. tCEZ, and tREZ must be satisfied for open circuit condition. tRCH or tRRH must be satisfied for a read cycle.
2. 3.
4.
5.
6.
7.
8. 9.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 16. Only SL version.
PEDD514265ESL-01 MSM514265E/ESL
Timing Chart
* Read Cycle
tRC tRAS tRP tCRP tCSH tRCD tRAD tRAL tASR tRAH tASC
Column
VIH RAS VIL
CAS
VIH VIL
tRSH tCAS
tCRP
tCAH
Address
VIH VIL VIH VIL VIH VIL
Row
tRCS tAA tROH tAOE tCAC tRAC
tRRH tRCH tREZ
WE
OE
tOEZ tCLZ
Valid Data-out
tCEZ
DQ
VOH VOL
Open
"H" or "L" * Write Cycle (Early Write)
RAS
VIH VIL tCRP tRCD tRAD
tRC tRAS tRP tCSH tRSH tCAS tRAL tCRP
CAS
VIH VIL tASR
tRAH
tASC
tCAH
Address
VIH VIL
Row
Column
tCWL tWCS tWP tWCH
WE
VIH VIL VIH VIL VIH VIL
tRWL
OE
tDS
Valid Data-in
tDH
Open
DQ
"H" or "L"
9/15
PEDD514265ESL-01 MSM514265E/ESL * Read Modify Write Cycle
tRWC tRAS tRP tCSH tRCD tRAD tRSH tCAS tCWL tRWL tCRP
RAS
VIH VIL tCRP
CAS
VIH VIL tASR
tRAH
tASC
Column
tCAH
Address
VIH VIL
Row
tRCS tRWD
tCWD
tWP
WE
VIH VIL VIH VIL tRAC tCLZ tCAC tOEZ
Valid Data-out
tAWD tAA tOEA tOED tDH tDS
Valid Data-in
tOEH
OE
DQ
VI/OH VI/OL
"H" or "L"
10/15
PEDD514265ESL-01 MSM514265E/ESL * Fast Page Mode Read Cycle (Part-1)
tRASP RAS VIH VIL tCRP CAS VIH VIL VIH VIL VIH VIL VIH VIL tOEA tCAC DQ VOH VOL tCLZ tAA tRAC tAA tCPA tDOH
Valid Data-out
tRP tHPC tRHCP tCP tCAS tCAS tASC tCAH
tRCD tCSH tCAS tASR
Row
tCP
tRAD tRAH tASC
tCAH
tASC
Column
tCAH
Address
Column
Column
tRCS WE tCHO tOEP tCAC tAA tOEA tOEZ
Valid Data-out
tOCH tOEP tOEA
tRRH
tCAC
OE
tOEZ
Valid * Data-out
tREZ
Valid * Data-out
* : Same Dada,
"H" or "L"
*
Fast Page Mode Read Cycle (Part-2)
tRASP RAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCAC tCAC DQ VOH VOL tCLZ tWEZ
Valid * Data-out
tRP tHPC tRHCP tCP tCAS tASC
Column
tRCD tCRP tCSH tCAS tASR
Row
tCP
tCAS tCAH
Column
CAS
tRAD tRAH tASC
tCAH
tASC
tCAH
Address
Column
tRCS WE tAA tRAC
tRCS tRCH tWPE tOEA
tAA
tCPA tAA
OE
tCAC
tDOH
Valid * Data-out
tCEZ
Valid * Data-out
* : Same Data,
"H" or "L"
11/15
PEDD514265ESL-01 MSM514265E/ESL * Fast Page Mode Write Cycle (Early Write)
tRASP RAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tDS DQ VIH VIL
Valid * Data-in
tRP tHPC tHPC tCP tCAS tRSH tCAS tCAH
tCSH tCRP tRCD tCAS tASR
Row
tCP
CAS
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
Address
Column
Column
Column
tWCS
tWCH
tWCS
tWCH
tWCS tWCH
WE
OE
tDH
tDS
Valid * Data-in
tDH
tDS
Valid * Data-in
tDH
"H" or "L" *
Fast Page Mode Read Modify Write Cycle
tRASP VIH RAS VIL VIH VIL tASR Address VIH VIL VIH VIL tRAC OE VIH VIL tCAC DQ VI/OH VI/OL tCLZ tOEZ
Valid * Data-out
tRWD tCRP tRCD tCWD tRAD tRAH
Column
tCPWD tCP tASC tHPRWC tCAH tCWL
Column
tRWL
CAS
tASC
tCAH tCPA
Row
tRCS WE tAWD tAA tOEA tOED tDH tDS
tRCS
tCWD tAWD
tWP
tDS
tWP
tOEH tCAC tCLZ tOEZ
Valid * Data-in
tOED tDH
Valid * Data-out
tOEH
Valid * Data-in
"H" or "L"
12/15
PEDD514265ESL-01 MSM514265E/ESL * RAS-Only Refresh Cycle
tRC RAS VIH VIL VIH VIL VIH VIL VOH VOL tASR tRAH
Row
tRAS tRP tCRP tRPC
CAS
Address
tCEZ DQ
Open
Note: WE, OE = "H" or "L"
"H" or "L"
*
CAS before RAS Refresh Cycle
tRP RAS VIH VIL VIH VIL tCEZ DQ VOH VOL tRPC tCP tCSR tCHR tRAS
tRC tRP tRPC
CAS
Open
Note: WE, OE, Address = "H" or "L"
13/15
PEDD514265ESL-01 MSM514265E/ESL * Hidden Refresh Read Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRP
tRAS tCRP tRCD
CAS
tASC
Column
tCAH
tRCS WE
tCAC tRAL tAA tROH tOEA
tRRH
tWRH tWRP
OE
VIH VIL
tOEZ DQ VOH VOL
Open
tRAC
tCLZ
Valid Data-out
"H" or "L" * Hidden Refresh Write Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRP
tRAS tCRP tRCD
CAS
tASC
Column
tCAH
tRAL tRWL tWP tWCS tWCH
WE
VIH VIL VIH VIL VIH VIL tDS
OE
tDH
Valid Data-in
DQ
"H" or "L"
14/15
PEDD514265ESL-01 MSM514265E/ESL CAS before RAS Self-Refresh Cycle
tRP RAS VIH VIL VIH VIL tCEZ DQ VOH VOL tRPC tCP CAS tCSR
tRASS
tRPS
tRPC tCHS
Open
Note: WE, OE, Address = "H" or "L" Only SL Version
"H" or "L"
15/15

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